1. Field of the Invention
The present invention relates to a method for the manufacture of an insulated gate field effect semiconductor device having a gate insulating layer member and a gate electrode.
2. Description of the Prior Art
Heretofore there has been proposed, an insulated gate field effect semiconductor device which comprises a substrate having its surface formed of a semiconductor of silicon, a gate insulating layer member formed on the substrate and being an insulating silicon oxide layer, and a gate electrode formed on the gate insulating layer member.
For the manufacture of the device of such a structure, it has been proposed to form, by a thermal oxidation process, the insulating silicon oxide layer which forms the gate insulating layer member.
The thermal oxidation process allows more ease in the formation of the insulating layer of silicon oxide, and hence facilitates the fabrication of the device.
In the case where the insulating silicon oxide layer is formed as the gate insulating layer member through the thermal oxidation technique, when the gate electrode is formed on the gate insulating layer, they react with each other. This imposes a certain limitation on the reduction of the thickness of the insulating silicon oxide layer or the gate insulating layer member. Hence there is a certain limit to the fabrication of the device with a small channel length and accordingly with excellent frequency characteristics.
As a solution to this problem, it has been proposed to form the gate insulating layer member by a first insulating silicon oxide layer which is deposited in contact with the substrate surface and a second insulating silicon nitride layer which is deposited on the first insulating silicon oxide layer.
Conventionally the first insulating silicon oxide layer is obtained by the thermal oxidation technique, as mentioned above, and a plasma CVD technique is employed for the formation of the second insulating silicon nitride layer.
In this instance, since the gate electrode is deposited on the second insulating silicon nitride layer, the gate insulating layer member and the gate electrode do not substantially react with each other. Therefore, the gate insulating layer member can be formed to a sufficiently small thickness. However, the deposition of the second insulating silicon nitride layer by the plasma CVD process on the first insulating silicon oxide layer inflicts damage on the latter. This introduces difficulties in forming the first and second insulating layers and consequently the gate insulating layer member homogeneously and to a uniform thickness through it. Accordingly, it is difficult to fabricate device of excellent characteristics.
It has also been proposed to employ a low-pressure CVD technique for the deposition of the second insulating silicon nitride layer so as to avoid the above problem that the first insulating silicon oxide layer is damaged by the plasma CVD process for the formation thereon of the second insulating silicon nitride layer.
In a device fabricated by such a method, however, the voltage-capacitance characteristics between the semiconductor of the substrate and the gate electrode has a large hysteresis characteristic. Consequently, the threshold voltage of the device drifts in accordance with voltage which is applied across the semiconductor and the gate electrode. Accordingly, the use of the low-pressure CVD process for the second insulating silicon nitride layer always leads to the defect that the device has the above-said threshold voltage drift.
Furthermore, another method for forming the gate insulating layer has been proposed in which a silicon oxide layer is formed on the silicon surface of the substrate and then the silicon oxide layer is heat treated at a high temperature of around 1200xc2x0 C. in an atmosphere of ammonia gas to thereby nitrify the surface of the silicon oxide layer so that the first insulating silicon oxide layer and the second insulating silicon nitride layer are formed.
With this method, it is possible to avoid the problem that is posed by the formation of the second insulating silicon nitride layer through the plasma CVD and the low-pressure CVD process. But the high temperature heat treatment for nitrifying the surface of the silicon oxide layer will inflict thermal damage on the substrate. Accordingly, a device of excellent characteristics cannot be obtained.
It is therefore an object of the present invention to provide a novel method for the manufacture of an insulated gate field effect semiconductor device having a gate insulating layer member and a gate electrode, and which is free from the above-said defects of the prior art.
According to the manufacturing method of the present invention, an insulating layer is formed as a layer constituting the gate insulating layer member by the photo CVD technique.
With the manufacturing method of the present invention, the insulating layer can be formed on the substrate in contact with its surface without inflicting any damage thereon. Further in the case of forming the insulating layer on the gate electrode, no damage will be inflicted on the gate electrode. Furthermore, in the case of forming the insulating layer as a second insulating layer on a first insulating layer, no damage will be inflicted on the latter.
In the case where the surface of the substrate is formed of silicon, the gate insulating layer member is composed of the first insulating silicon oxide layer and the second insulating silicon or aluminum nitride layer formed by the photo CVD technique, the deposition of the second insulating silicon or aluminum nitride layer by the photo CVD process will inflict substantially no damage on the first insulating silicon oxide layer. Moreover, since the deposition of the second insulating silicon or aluminum nitride layer by the photo CVD process does not involve any high-temperature heat treatment, no thermal damage will be caused to the semiconductor of the substrate. Besides when the gate electrode is formed on the gate insulating layer member, since it is formed on the silicon or aluminum nitride layer, they will show substantially no reactions with each other. Furthermore the voltage-capacitance characteristics between the semiconductor of the substrate and the gate electrode have not a large hysteresis characteristics.